1. Field of the Invention
The present invention relates to a method for fabricating a capacitor, and more particularly, to a method for fabricating a metal-insulator-metal capacitor.
2. Description of the Prior Art
The manufacturing of semiconductor devices frequently requires the creation of electrical components that collectively perform functions of data manipulation (logic functions) or functions of data retention (storage functions). Most semiconductor devices are devices that perform binary logic functions that are reflected by on or off-mode conditions of binary circuits. It is therefore not uncommon to see a mixture of electrical components and functions, comprising semiconductor devices, resistors, and capacitors. The majority of semiconductor components consists of transistors, gate electrodes, and a variety of switching components for the performance of logic processing functions. Capacitors may form a basic component of analog circuits in for instance switched capacitor filters. Capacitors are further widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits.
A capacitor may be used as part of analog processing capabilities and in digital circuits, the capacitor is used to provide charge storage locations for individual bits of digital data that are stored in the digital Integrated Circuit (IC). The conventional process of creating a capacitor in combination with the creation of a CMOS device is a relatively complex and expensive process. Hence, a Metal-Insulator-Metal (MIM) capacitor that can be applied for mix-mode applications, is often used as a relatively simple and therefore cost effective method of creating a capacitor.
U.S. Pat. No. 6,746,914 shows a method of applying the damascene processes as part of the creation of an MIM capacitor. Please refer to FIG. 1. FIG. 1 shows a cross section of a conventional MIM capacitor. According to the conventional method, a substrate 10 is first provided, in which semiconductor devices have been created in or over the surface of the substrate. Next, a first dielectric layer 12 is disposed over the surface of the substrate 10. Next, a first dual damascene conductor 14 and a second dual damascene conductor 16 are created through the first dielectric layer 12. Next, an MIM capacitor is formed over the surface of the first dual damascene conductor 14, in which the MIM capacitor includes a bottom plate 18, an insulating layer 20, and a top plate 22. Next, an etch stop layer 24 is deposited on the first dielectric layer and the MIM capacitor, and a second dielectric layer 26 is then deposited thereon. A third dual damascene conductor 28 and a fourth dual damascene conductor 30 are formed through the second dielectric layer 26, in which the third dual damascene conductor 28 is aligned with the MIM capacitor and the fourth dual damascene conductor 30 is aligned with the second dual damascene conductor 16. Finally, a chemical mechanical polishing (CMP) process is performed for polishing the surface of the second dielectric layer and removing excess metal from the surface.
Despite the fact that the conventional method is able to successfully create an MIM capacitor with the incorporation of dual damascene processes, the fabrication of multiple dual damascene conductors is nevertheless complex, hence how to simplify the fabrication process of MIM capacitors and improve its overall efficiency and performance has become a widely studied topic in this field.